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3-47 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 TC530 tc534 5v precision data acquisition subsystems evaluation kit available TC530/534-3 11/14/96 features n precision (up to 17 bits) a/d converter n 3 wire serial port n flexible: user can trade-off conversion speed against resolution n single supply operation n C5v output pin n 4 input, differential analog mux (tc534) n automatic input polarity and overrange detection n low operating current ............................ 5ma max n wide analog input range ...................... 4.2v max n cost effective ordering information part no. package temp. range TC530coi 28-pin soic 0 c to +70 c TC530cpj 28-pin plastic dip (300 mil.) 0 c to +70 c tc534ckw 44-pin pqfp 0 c to +70 c tc534cpl 40-pin plastic dip 0 c to +70 c TC530ev evaluation kit for TC530/534 functional block diagram general description the TC530/534 are serial analog data acquisition sub- systems ideal for high precision measurements (up to 17 bits plus sign). the TC530 consists of a dual slope integrating a/d converter, negative power supply generator and 3 wire serial interface port. the tc534 is identical to the TC530, but adds a four channel differential input multiplexer. key a/d converter operating parameters (auto zero and integration time) are programmable, allowing the user to trade-off conversion time for resolution. data conversion is initiated when the reset input is brought low. after conversion, data is loaded into the output shift register and eoc is asserted indicating new data is available. the converted data (plus overrange and polarity bits) is held in the output shift register until read by the processor, or until the next conversion is completed allowing the user to access data at any time. the TC530/534 timebase can be derived from an exter- nal crystal of 2mhz (max), or from an external frequency source. the TC530/534 requires a single 5v power supply and features a C 5v, 10ma output which can be used to supply negative bias to other components in the system. a0 a1 osc in eoc r/w d in d out d clk osc out osc reset cap + cap c az tc05 TC530 tc534 c ref r int c int tc534 (only) (TC530 only) dc-to-dc converter state machine serial port negative supply output oscillator ( 4) dual slope a/d converter .01 f 0.01 f optional power-on reset cap 100k 10k +5v dif. mux (tc534 only) ch1 ch1 ch2 ch2 ch3 ch3 ch4 ch4 v in v in in in ab cmptr buf int c az v ref + v ref + c ref c ref acom + + + + + v dd v dd v dd v dd v ss +
3-48 telcom semiconductor, inc. electrical characteristics: v dd = v ccd , c az = c ref = 0.47 m f, unless otherwise specified. t a = +25 c t a = 0 c to +70 c symbol parameter test conditions min typ max min typ max unit analog r resolution note 1 17 17 bits zse zero-scale error 0.5 0.005 0.012 % f.s. with auto zero phase enl end point linearity note 1 and 2 0.015 0.030 0.015 0.045 % f.s. nl max deviation from best notes 1 and 2 0.008 0.015 % f.s. straight line fit zs tc zero-scale temperature 1 2 m v/ c coefficient sye roll-over error note 3 .012 .03 % f.s. fs tc full-scale temperature ext. v ref 10 ppm/ c coefficient tc = 0ppm/ c i in input current v in = 0v 6 pa v cmr common-mode v ss + 1.5 v dd C 1.5 v ss + 1.5 v dd C 1.5 v voltage range v int integrator output swing v ss + 0.9 v dd C 0.9 v ss + 0.9 v dd C 0.9 v v in analog input signal range v ss + 1.5 v dd C 1.5 v ss + 1.5 v dd C 1.5 v v ref voltage reference range v ss + 1 v dd C 1 v dd + 1 v dd C 1 v t d zero crossing comparator 2.0 3.0 m sec absolute maximum ratings* supply voltage ........................................................... +6v analog input voltage (v + in or v C in ) ....................... v dd to v ss logic input voltage ................. (v dd + 0.3v) to (gnd C 0.3v) ambient operating temperature range plastic dip package .............................................. (c) 0 c to +70 c soic package (c) .............................. 0 c to +70 c pqfp package (c) .............................. 0 c to +70 c storage temperature range .................... C 65 c to +150 c lead temperature (soldering, 10 sec) ..................... +300 c *stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = +25 c t a = 0 c to +70 c symbol parameter test conditions min typ max min typ max unit v dd analog power supply voltage 4.5 5.0 5.5 4.5 5.5 v v ccd digital power supply voltage 4.5 5.0 5.5 4.5 5.5 v p d TC530/534 total power v dd = v ccd = 5v 25 mw dissipation i s supply current (v s + p in ) 1.8 2.5 3.0 ma i ccd supply current (v ccd p in )f osc = 1mhz 1.5 1.7 ma 5v precision data acquisition subsystems TC530 tc534
3-49 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 5v precision data acquisition subsystems TC530 tc534 electrical characteristics: serial port interface: v ccd = +5v, unless otherwise specified. t a = +25 c t a = 0 c to +70 c symbol parameter test conditions min typ max min typ max unit v ih input logic high level 2.5 2.5 v v il input logic low level 0.8 0.8 v i in input current (di, do, d clk ) 10 m a v ol logic low output voltage i out = 250 m a 0.2 0.3 0.35 v (eoc) electrical characteristics: serial port interface: v ccd = +5v, unless otherwise specified. t a = +25 c t a = 0 c to +70 c symbol parameter test conditions min typ max min typ max unit tr, tf rise and fall times c l = 10pf 250 250 nsec (eoc, di, do) f xtl crystal frequency 2.0 2.0 mhz f ext external frequency on osc in 4.0 4.0 mhz t rs read setup time 1 1 m sec t rd read delay time 250 250 nsec t drs d clk to d out delay 450 450 nsec t pwl d clk low pulse width 150 150 nsec t pwh d clk high pulse width 150 150 nsec t dr data ready delay 200 200 nsec electrical characteristics: dc/dc converter section: v dd = +5v, unless otherwise specified. t a = +25 c t a = 0 c to +70 c symbol parameter test conditions min typ max min typ max unit r out output resistance i out = 10ma 65 85 100 w f clk oscillator frequency c osc = 0 100 khz i out v ss output current 10 10 ma electrical characteristics: multiplexer: v dd = +5v (note 4) , unless otherwise specified. t a = +25 c t a = 0 c to +70 c symbol parameter test conditions min typ max min typ max unit v inmax maximum input voltage C 2.5 2.5 C2.5 2.5 v r ds on drain/source on resistance 6 10 k w notes: 1. integrate time 3 66msec, auto zero time 3 66msec, v int (pk) = 4v. 2. end point linearity at z\v , z\x , c\v f.s. after full scale adjustment. 3. roll-over error is related to capacitor used for c int (see "recommended suppliers for c int ", table 2). 4. tc534 only.
3-50 telcom semiconductor, inc. pin configurations 1 2 3 4 20 19 18 5 6 7 8 17 23 22 21 9 10 11 12 24 25 26 27 28 TC530cpj 16 15 13 14 v v ccd d out d clk c ref c int c az buf acom c ref ref v ref + + cap agnd reset n/c eoc osc cap + 28 25 24 23 22 21 20 19 18 17 27 26 TC530coi osc out osc in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 33 32 31 30 29 28 27 26 25 24 23 2 3 4 5 6 7 8 9 10 11 16 15 v in d in r/w + v in dgnd n/c v v ss v ss v ss c ref c int c az buf acom c ref ref v ref + + osc out v in + v in dgnd n/c v c ref c int c az buf acom c ref ref v ref + + osc out osc out dgnd dgnd v ccd d out d clk cap agnd reset nc eoc osc cap v ccd v ccd cap agnd agnd reset reset osc osc n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c + cap + cap cap + osc in d in r/w tc534cpl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 tc534ckw a1 a1 a0 a0 osc in osc in d out d out d clk d clk eoc n/c n/c n/c d in d in r/w r/w eoc ch1 + ch2 + ch3 + ch3 + ch2 + ch1 + ch4 + ch4 ch3 ch2 ch1 v c ref acom c ref ref + v ref + ch4 + ch4 ch3 ch2 ch1 12 13 14 15 44 43 42 41 39 38 40 n/c c int 37 36 35 34 16 17 18 19 20 21 22 buf c az n/c n/c v dd v dd v dd v ss v dd 12 13 14 15 5v precision data acquisition subsystems TC530 tc534
3-51 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 pin description pin no. pin no. pin no pin no. (TC530 (TC530 (tc534 (tc534 28-pin 28-pin 40-pin 44-pin pdip, 300 mil.) soic) pdip) pqfp) symbol description 11140v ss analog output. negative power supply converter output and reservoir capacitor connection. this output can be used to provide negative bias to other devices in the system. 22241c int analog output. integrator capacitor connection and integrator output. 33342c az analog input. auto zero capacitor connection. 4 4 4 43 buf analog output. integrator capacitor connection and voltage buffer output. 5 5 5 2 acom analog input. this pin is ground for all of the analog switches in the a/d converter. it is grounded for most applications. acom and the input common pin (v C in or chx C ) should be within the common mode range, cmr. 6663c C ref analog input. reference cap negative connection. 7774c + ref analog input. reference cap positive connection. 8885v C ref analog input. external voltage reference negative connection. 9996v + ref analog input. external voltage reference positive connection. not used not used 10 7 ch4 C analog input. multiplexer channel 4 negative differential analog input. not used not used 11 8 ch3 C analog input. multiplexer channel 3 negative differential analog input. not used not used 12 9 ch2 C analog input. multiplexer channel 2 negative differential analog input. not used not used 13 10 ch1 C analog input. multiplexer channel 1 negative differential analog input. not used not used 14 11 ch4 + analog input. multiplexer channel 4 positive differential analog input. not used not used 15 12 ch3 + analog input. multiplexer channel 3 positive differential analog input. not used not used 16 13 ch2 + analog input. multiplexer channel 2 positive differential analog input. not used not used 17 14 ch1 + analog input. multiplexer channel 1 positive differential analog input. 10 10 not used not used v C in analog input. negative differential analog voltage input. 11 11 not used not used v + in analog input. positive differential analog voltage input. 12 12 18 15 dgnd analog input. ground connection for serial port circuit. not used not used 19 16 a1 logic level input. multiplexer address msb. not used not used 20 17 a0 logic level input. multiplexer address lsb. 14 14 21 18 osc out analog input. timebase for state machine. this pin connects to one side of an at-cut crystal having an effective series resistance of 100 w (typ) and a parallel capacitance of 20pf if an external frequency source is used to clock the TC530/534, this pin must be left floating. 5v precision data acquisition subsystems TC530 tc534
3-52 telcom semiconductor, inc. 5v precision data acquisition subsystems TC530 tc534 pin description (cont.) pin no. pin no. pin no pin no. (TC530 (TC530 (tc534 (tc534 28-pin 28-pin 40-pin 44-pin pdip, 300 mil.) soic) pdip) pqfp) symbol description 15 15 22 19 osc in analog input. this pin connects to the other side of the crystal described in osc out above. the TC530/534 may also be clocked from an external frequency source connected to this pin. the external frequency source must be a pulse wave form with a minimum 30% duty cycle and rise and fall times 15nsec (max). if an external frequency source is used, osc out must be left floating. a maximum operating frequency of 2mhz (crystal) or 4mhz (external clock source) is permitted. 16 16 23 20 d out logic level output. serial port data output pin. this pin is enabled only when r/w is high. 17 17 24 21 d clk logic input, positive and negative edge triggered. serial port clock. when r/w is high, serial data is clocked out of the TC530/534a (on d out ) at each high-to-low transition of d clk . a/d initialization data (load value) is clocked into the TC530/534 (on d in ) at each low-to-high transition of d clk . a maximum serial port d clk frequency of 3mhz is permitted. 18 18 25 22 d in logic level input. serial port input pin. the a/d converter integration time (t int ) and auto zero time (t az ) values are determined by the load value byte clocked into this pin. this initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. the load value is clocked into d in msb first. 19 19 26 23 r/w logic level input. this pin must be brought low to perform a write to the serial port (e.g. initialize the a/d converter). the d out pin of the serial port is enabled only when this pin is high. 20 20 27 24 eoc open drain output. end-of-conversion (eoc) is asserted any time the TC530/534 is in the az phase of conversion. this occurs when either the TC530/534 initiates a normal az phase, or when reset is pulled high. eoc is returned high when the TC530/534 exits az. since eoc is driven low immediately following completion of a conversion cycle, it can be used as a data ready processor interrupt. 21 21 30 28 reset logic level input. it is necessary to force the TC530/534 into the auto zero phase when power is initially applied. this is accomplished by momentarily taking reset high. using an i/o port line from the microprocessor, or by applying an external system reset signal, or by connecting a 0.01 m f capacitor from the reset input to v ss . conversions are performed continuously as long as reset is low and conversion is halted when reset is high. reset may therefore be used in a complex system to momentarily suspend conversion (for example while the address lines of an input multiplexer are changing state). in this case, reset should be pulled high only when the eoc is low to avoid excessively long integrator discharge times which could result in erroneous conversion (see applications section).
3-53 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 5v precision data acquisition subsystems TC530 tc534 figure 1. serial port timing t rd t rs t drs t pwl r/w read timing read format write format write timing write default timing eoc d out d clk r/w eoc d out d clk eoc sgn msb lsb ovr t ls t dls t pwl r/w d in d clk t ldl t lds r/w d in r/w d out d clk msb lsb for polled vs interrupt operation and write value modified cycle use tc520a data sheet figure 1 & 2. pin description (cont.) pin no. pin no. pin no pin no. (TC530 (TC530 (tc534 (tc534 28-pin 28-pin 40-pin 44-pin pdip, 300 mil.) soic) pdip) pqfp) symbol description 22 22 32 30 v ccd analog input. power supply connection for digital logic and serial port. proper power-up sequencing is critical, see the applications section. 23 23 34 32 osc input. the negative power supply converter normally runs at a frequency of 100khz. this frequency can be slowed down to reduce quiescent current by connecting an external capacitor between this pin and v + s . (see typical characteristics ). 25 25 37 35 v dd analog input. power supply connection for the a/d analog section and dc-dc converter. proper power-up sequencing is critical, see the applications section. 26 26 38 36 cap + analog input. storage capacitor positive connection for the dc/dc converter. 27 27 39 37 agnd analog input. ground connection for dc/dc converter. 28 28 40 38 cap C analog input. storage capacitor negative connection for the dc/dc converter. 13, 24 13, 24 28, 29, 31, 1, 25, 26, 27 nc no connect. do not connect any signal to these pins. 33, 35, 36 29, 31, 33, 34, 39, 44,
3-54 telcom semiconductor, inc. 30 20 10 0 0.1/t 1/t 10/t input frequency normal mode rejection (db) t = measurement period eoc t dr az updated data ready updated data ready int d int iz az conversion phase data to serial port transmit register figure 3. integrating converter normal mode rejection figure 2. a/d converter timing detailed description dual slope integrating converter the TC530/534 dual slope converter operates by inte- grating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the integrator output to cross 0v (deintegrating). the resulting count is read as conversion data. a simple mathematical expression that describes dual slope conversion is: (1) integrate voltage = deintegrate voltage (2) t int 0 t dint 0 1/r int c int v in (t)dt = 1/r int c int v ref from which: (3) [] (t int ) (v in ) = (v ref ) (r int )(c int ) [] (t dint ) (r int )(c int ) and therefore: (4) v in = v ref [] t dint t int where: v ref = reference voltage t int = integrate time t dint = reference voltage deintegrate time inspection of equation (4) shows dual slope converter accuracy is unrelated to integrating resistor and capacitor values, as long as they are stable throughout the measure- ment cycle. this measurement technique is inherently ratiometric (i.e., the ratio between the t int and t dint times is equal to the ratio between v in and v ref ). another inherent benefit is noise immunity. input noise spikes are integrated (or averaged to zero) during the integration period. the integrating converter has a noise immunity with an attenuation rate of at least C20db per decade. interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. for this reason, the integration period of the converter is often established to reject 50/60hz line noise. the ability to reject such noise is shown by the plot of figure 3. in addition to the two phases required for dual slope measurement (integrate and deintegrate), the TC530/534 performs two additional adjustments to minimize measure- ment error due to system offset voltages. the resulting four internal operations (conversion phases) performed each measurement cycle are: auto zero (az), integrator output zero (iz), input integrate (int) and reference deintegrate (d int ). the az and iz phases compensate for system offset errors and the int and d int phases perform the actual a/d conversion. 5v precision data acquisition subsystems TC530 tc534
3-55 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 auto zero phase (az) this phase compensates for errors due to buffer, inte- grator and comparator offset voltages. during this phase, an internal feedback loop forces a compensating error voltage on auto zero capacitor (c az ). the duration of the az phase is programmable via the serial port (see also programming az and int phase duration paragraph of this document). input integrate phase (int) in this phase, a current directly proportional to differen- tial input voltage is sourced into integrating capacitor c int . the amount of voltage stored on c int at the end of the int phase is directly proportional to the applied differential input voltage. input signal polarity (sign bit) is determined at the end of this phase. converter resolution and conversion speed is a function of the duration of the int phase, which is programmable by the user via the serial port (see also programming az and int phase duration paragraph of this document). the shorter the integration time, the faster the speed of conversion, but the lower the resolution. con- versely, the longer the integration time, the greater the resolution, but at slower the speed of conversion. reference deintegrate phase (dint) this phase consists of measuring the time for the integrator output to return (at a rate determined by the external reference voltage) from its initial voltage to 0v. the resulting timer data is stored in the output shift register as converted analog data. integrator output zero phase (iz) this phase guarantees the integrator output is at zero volts when the az phase is entered so that only true system offset voltages will be compensated for. all internal converter timing is derived from the fre- quency source at osc in and osc out . this frequency source must be either an externally provided clock signal, or an external crystal. if an external clock is used, it must be connected to the osc in pin and the osc out pin must remain floating. if a crystal is used, it must be connected between osc in and osc out and physically located as close to the osc in and osc out pins as possible. in either case, the incoming clock frequency is divided by four and the resulting clock serves as the internal TC530/534 timebase. applications programming the TC530/534 az and int phase duration: these two phases have equal duration determined by the crystal (or external) frequency and the timer initialization byte (load value). timing is selected as follows: (1) select integration time integration time must be picked as a multiple of the period of the line frequency. for example, t int times of 33msec, 66msec and 132msec maximize 60hz line rejection. (2) estimate crystal frequency crystal frequencies as high as 2mhz are allowed. crystal frequency is estimated using: f in = 2(r) t int where: r = desired converter resolution (in counts) f in = input frequency (in mhz) int = integration time (in seconds) (3) calculate load value [load value] 10 = 256 1024 (t int )(f in ) f in can be adjusted to a standard value during this step. the resulting base -10 load value must be converted to a hexadecimal number, then loaded into the serial port prior to initiating a/d conversion. d int and iz phase timing the duration of the d int phase is a function of the amount of voltage stored on the integrator capacitor during int, and the value of v ref . the d int phase is initiated immediately following int and terminated when an integra- tor output zero-crossing is detected. in general, the maxi- mum number of counts chosen for d int is twice that of int (with v ref chosen at v in (max)/2). system reset the TC530/534 must be forced into the az state when power is first applied. a .01 m f capacitor connected from reset to v cc (or external system reset logic signal) can be used to momentarily drive reset high for a minimum of 100msec. selecting component values for the TC530/534 (1) calculate integrating resistor (r int ) the desired full-scale input voltage and amplifier output current capability determine the value of r int . the buffer and integrator amplifiers each have a full- scale current of 20 m a. the value of r int is therefore directly calculated as follows: 5v precision data acquisition subsystems TC530 tc534
3-56 telcom semiconductor, inc. 5v precision data acquisition subsystems TC530 tc534 20 v inmax r int (m ) = where: v inmax = maximum input voltage (full count voltage) r int = integrating resistor (in m w ) for loop stability, r int should be 3 50k w . (2) select reference (c ref ) and auto zero (c az ) capacitors c ref and c az must be low leakage capacitors (such as polypropylene). the slower the conversion rate, the larger the value c ref must be. recommended capacitors for c ref and c az are shown in table 1. larger values for c az and c ref may also be used to limit roll-over errors. table 1. c ref and c az selection conversions typical value of suggested * per second c ref , c az ( m f) part number >7 0.1 wima mk12 .1/63/20 2 to 7 0.22 wima mk12 .22/63/20 2 or less 0.47 wima mk12 .47/63/20 *wima corp. listing on the last page of this data sheet. 3. calculate integrating capacitor (c int ) the integrating capacitor must be selected to maxi- mize integrator output voltage swing. the integrator output voltage swing is defined as the absolute value of v dd (or v ss ) less 0.9v (i.e. |v dd C 0.9v| or |v ss + 0.9v|). using the 20 m a buffer maximum output current, the value of the integrating capacitor is calculated using the following equation: (v s ?0.9) (t int )(20) c int ( f) = where: t int = integration period v s = applied supply voltage c int = integrator capacitor value (in m f) it is critical that the integrating capacitor have a very low dielectric absorption. pps capacitors are an example of one such chemistry. table 2 summa- rizes various capacitors suitable for c int . value suggested part number* 0.1 wima mk12 .1/63/20 0.22 wima mk12 .22/63/20 0.33 wima mk12 .33/63/20 0.47 wima mk12 .47/63/20 *wima corp. listing on the last page of this data sheet. 4. calculate v ref the reference deintegration voltage is calculated using: v ref (in volts) = (v s ?0.9)(c int )(r int ) 2(t int ) serial port communication with the TC530/534 is accomplished over a 3 wire serial port. data is clocked into d in on the rising edge of d clk and clocked out of d out on the falling edge of d clk . r/w must be high to read converted data from the serial port and low to write the load value to the TC530/ 534. load value write cycle (figure 4) following the power-up reset pulse, the load value (which sets the duration of az and int) must next be transmitted to the serial port. to accomplish this, the proces- sor monitors the state of eoc (which is available as a hardware output or at d out ). r/w is taken low to initiate the write cycle only when eoc is low (during the az phase). (failure to observe eoc low may cause an offset voltage to be developed across c int resulting in erroneous readings). the 8 bit load value data on d in is clocked in by d clk . the processor then terminates the write cycle by taking r/w high. (data is transferred from the serial input shift register to the time base counter on the rising edge of r/w, and data conversion is initiated). data read cycle (figure 5) data is shifted out of the serial port in the following order: end of conversion (eoc), overrange (ovr), sign (sgn), conversion data (msb first). when r/w is high, the state of the eoc bit can be polled by simply reading the state of d out . this allows the processor to determine if new data is available without connecting an additional wire to the eoc output pin (this is especially useful in a polled environment). input multiplexer (tc534 only) a 4 input, differential multiplexer is included in the tc534. the states of channel address lines a0 and a1 determine which differential v in pair is routed to the con- table 2. recommend capacitor for c int
3-57 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 5v precision data acquisition subsystems TC530 tc534 verter input. a0 is the least significant address bit (i.e., channel 1 is selected when a0 = 1 and a1 = 0). the multiplexer is designed to be operated in a differential mode. for single-ended inputs, the chx C input for the channel under selection must be connected to the ground reference associated with the input signal. eoc r/w reset d clk d in 1 1001111 az az load value msb lsb int dint iz az conversion phase timing status converter held in az state due to reset = 1 write load value to serial port power-up reset undefined converter in normal service r/w brought low during az for serial port write cycle r/w = high strobes load value into timebase and starts conversion continuous conversions figure 4. TC530/534 initialization and load value write cycle eoc ovr pol msb lsb r/w d clk d out figure 5. serial port data read cycle dc/dc converter an on-board, tc7660h-type charge pump supplies negative bias to the converter circuitry, as well as to external devices. the charge pump develops a negative output voltage by moving charge from the power supply to the reservoir capacitor at v ss by way of the commutating capacitor connected to the cap + and cap C inputs. the charge pump clock operates at a typical frequency of 100khz. if lower quiescent current is desired, the charge pump clock can be slowed by connecting an external ca- pacitor from the osc pin to v dd . reference typical charac- teristics curves. applications design example figure 6 shows a typical tc534 interrupt-driven applica- tion. timing and component values are calculated from equations and recommendations made in the dual slope integrating converter and programming the TC530/534 sections of this document. the eoc connection to the processor int input is for interrupt-driven applications only. (in polled systems, the eoc output is available on d out ). given required resolution: 16 bits (65,536 counts.) maximum v in : 2v power supply voltage: +5v 60hz system 1. pick integration time (t int ) 66msec 2. estimate crystal frequency f in = 2r/t int = 2 x 65536/66 x 10 C3 = 1.98mhz (use 2mhz)
3-58 telcom semiconductor, inc. 5v precision data acquisition subsystems TC530 tc534 figure 6. TC530/534 typical application a0 a1 reset eoc v ccd v ccd v dd v dd d out d clk x1: 2mhz r2 100k r1 100k 100 1 f tc04 (1.25v v ref ) (1.03v) d in r/w acom osc in osc out v ss dgnd c az c az 0.22 f c in 0.33 f r i nt 100k tc534 c int analog inputs channel control c1 .01 f 10 f mux in1 + in1 in2 + in2 in3 + in3 in4 + in4 +5v +5v ?v (optional) buf v ref + v ref + c ref c ref c ref 0.22 f + cap cap 1 f +5v int processor i/o i/o i/o i/o .01 f .01 f 1 f 3. calculate load value load value = 256 C (t int )(f in )/1024 = [128] 10 [128] 10 = 80 hex 4. calculate r int r int (in m w ) = v inmax /20 = 2/20 = 100k w 5. calculate c int for maximum (4v) integrator out- put swing c int (in m f) = (t int )(20 x 10 C6 )/ (v s C 0.9) = (.066)(20 x 10 C6 )/(4.1) = .32 m f (use closest value: 0.33 m f) note: telcom recommended capacitor: wima p/n: mk12 .33/63/10 6. choose c ref and c az based on conversion rate conversions/sec = 1/(t az + t int + 2t int + 2msec) = 1/(66msec + 66msec + 132msec + 2msec) = 3.7 conversions/sec from which c az = c ref = 0.22 m f (see table 1) note: telcom recommended capacitor: wima p/n: mk12 .22/63/10 7. calculate v ref v ref (in volts = (v s C 0.9)(c int )(r int ) 2(t int ) = (4.1)(0.33x10 C6 )(10 5 )/2(.066) = 1.025v power supply sequencing improper sequencing of the power supply inputs (v dd vs. v ccd ) can potentially cause an improper power-up sequence to occur. see circuit design/layout consider- ations below. failing to insure a proper power-up sequence can cause spurious operation. ciruit design/layout considerations (1) separate ground return paths should be used for the analog and digital circuitry. use of ground planes and trace fill on analog circuit sections is highly recommended except for in and around the integrator section and c ref , c az . (c int , c ref , c az , r int ). stray capacitance be- tween these nodes and ground appears in parallel with the components themselves and can affect measurement accu- racy.
3-59 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 5v precision data acquisition subsystems TC530 tc534 TC530ev evaluation kit the TC530ev consists of a 4" x 6" pre-assembled circuit board that connects to the serial port of any pc or dumb terminal. also included is a windows tm* excel tm* -based design utility that calculates component and load values based on user input, and prints a finished circuit schematic. please contact your local telcom representative for more information, or point your web browser to http://www.telcom- semi.com. (2) improper sequencing of the power supply inputs (v dd vs. v ccd ) can potentially cause an improper power-up sequence to occur in the internal state machines. it is recommended that the digital supply, v ccd , be powered up first. one method of insuring the correct power-up sequence is to delay the analog supply using a series resistor and a capacitor. see figure 6, TC530/534 typical application. (3) decoupling capacitors, preferably a higher value elec- trolytic or tantulum in parallel with a small ceramic or tantalum, should be used liberally. this includes bypassing the supply connections of all active components and the voltage reference. (4) critical components should be chosen for stability and low noise. the use of a metal-film resistor for r int and polypropylene or polyphenelyne sulfide (pps) capacitors for c int , c az , and c ref is highly recommended. (5) the inputs and integrator section are very high imped- ance nodes. leakage to or from these critical nodes can contribute measurement error. a guard-ring should be used to protect the integrator section from stray leakage. (6) circuit assemblies should be scrupulously clean to prevent the presence of contamination from assembly, handling, or the cleaning itself. minutely conductive trace contaminates, easily ignored in most applications, can ad- versely affect the performance of high impedance circuits. the input and integrator sections should be made as com- pact and close to the tc53x as possible. (7) digital and other dynamic signal conductors should be kept as far from the tc53xs analog section as possible. the microcontroller or other host logic should be kept quiet during a measurement cycle. background activites such as keypad scanning, display refreshing, and power switching can introduce noise. *all trademarks are the property of their respective owners.
3-60 telcom semiconductor, inc. typical characteristics load current (ma) output current (ma) ? ? ? ? ? 0 1 2 3 4 5 010203040 50 60 70 0 6 8 10 4 2141618 12 20 80 output voltage (v) output voltage vs load current ? ? ? ? ? ? ? ? ? output voltage (v) output voltage vs. output current oscillator capacitance (pf) 100 10 1 110 100 1000 oscillator frequency (khz) oscillator frequency vs. capacitance load current (ma) 0 3 456 12 78 910 0 25 50 75 100 125 150 175 200 output ripple (mv pk-pk) output ripple vs. load current temperature ( c) 70 80 90 100 60 50 40 ?0 025 ?5 50 75 100 output source resistance ( w ) output source resistance vs. temperature t a = 25 c v + = 5v t a = +25 c v + = 5v t a = 25 c slope 60 w v + = 5v, t a = 25 c osc. freq. = 100khz cap = 1 f cap = 10 f v + = 5v i out = 10ma temperature ( c) 125 150 100 75 50 ?0 025 ?5 50 75 125 100 oscillator frequency (khz) oscillator frequency vs. temperature v + = 5v 5v precision data acquisition subsystems TC530 tc534
3-61 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 wima corporation capacitor representatives (tables 1 and 2) malaysia: ma electronics (m) sdn bhd 346-b jalan jelutong 11600 penang tel.: 6 04-2 81 45 18 fax: 6 04-2 81 45 15 singapore: microtronics assoc. (pte.) ltd. 8, lorong bakar batu 03-01, kolam ayer ind. park singapore 1334 tel.: 65-7 48-18 35 tlx: 34 929 fax: 65-7 43-30 65 south africa: kopp electronics limited p.o. box 3853 2128 rivonia tel.: 0 11-4 44-23 33 fax: 0 11-4 44-17 06 south korea: yong jun electronic co. #201, sungwook bldg. 1460-16, seocho-dong seocho-ku seoul, korea tel.: 2-52 31 80 02 fax: 2-5 23 18 03 taiwan, r.o.c.: solomon technology corp. 7th floor no. 2 lane 47, sec. 3 nan kang road taipei tel.: 8 86-2-7 88 89 89 fax: 8 86-2-7 88 82 75 thailand: microtronics thai ltd. 50/68 t.t. court cheng wattana road amphur pak-kreed nonthaburi 11120 tel.: 6 62-5 84 58 07, ext. 102 fax: 6 62-5 83 37 75 usa: the inter-technical group, inc. wima division 175 clearbrook road p.o. box 535 elmsford, ny 10523-0535 tel.: 914-347-2474 fax: 914-347-7230 taw electronics, inc. 4215, w. burbank, blvd. burbank, ca, 91505 tel.: 8 18-8 46-39 11 fax: 8 18-8 46-11 94 venezuela: magnetica, s.a. apartado 78117 caracas 1074 a tel.: 58-2-2 41 75 09 fax: 58-2-2 41 55 42 australia: adilam electronics (pty.) ltd. p.o. box 664 3 nicole close bayswater 3153 tel.: 3-7 61 44 66 fax: 3-7 61 41 61 canada: r-theta inc. 130 matheson blvd. east, unit 2 mississauga, ont. l4z1y6 tel.: 9 05-8 90-02 21 fax: 9 05-8 90-16 28 hong kong: realtronics co. ltd. e-3, hung-on building 2, king's road tel.: 25 70 11 51 fax: 28 06 84 74 india: susan agencies p.o. box 2138 srirampuram p.o. bangalore-560 021 tel.: 0 80-3 32 06 62 fax: 0 80-3 32 43 38 israel: m.g.r. technology p.o. box 2229 rehavot 76121 tel.: 9 72-8-41 17 19 fax: 9 72-8-41 41 78 japan: unidux inc. 5-1-21, kyonan-cho musashino-shi tokyo 180 tel.: 04 22-32-41 11 fax: 04 22-32-03 31 5v precision data acquisition subsystems TC530 tc534

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